A conventional voltage comparator is provided with, for example, as shown in FIG. 4, a plus-side input terminal 1, a minus-side input terminal 2, an output terminal 3, and a differential amplifier 20 composed of MOS transistors 21 through 24. The following will describe the operation of the above-mentioned members.
In general, in a voltage comparator, when the potential of the plus-side input terminal 1 is V.sub.IN1, the potential of the minus-side input terminal 2 is V.sub.IN2. power source potentials are respectively V.sub.DD and V.sub.SS, and the gain of the voltage comparator as an amplifier circuit is G, an output voltage V.sub.OUT generated at the output terminal 3 is given by the equation: EQU V.sub.OUT =G{(V.sub.IN1 -V.sub.IN2)}+V.sub.REF
Note that, the V.sub.REF in the equation is generally referred to as a reference voltage. The reference voltage V.sub.REF normally takes a potential value of a medium of the power source potentials V.sub.DD and V.sub.SS. EQU V.sub.REF =(V.sub.DD -V.sub.SS)/2
However, the reference voltage V.sub.REF may take a value different from the specified one.
This allows a voltage in accordance with the difference between the two input terminals 1 and 2 to be outputted from the output terminal 3. In the case where the two inputs have the same potential, the reference voltage V.sub.REF is outputted.
However, in the case where an actual voltage comparator is not provided with an offset compensating circuit 10 of FIG. 4, when the properties of the MOS transistors 21 through 24 constituting the differential amplifier 20 are non-uniform, the reference voltage V.sub.REF is outputted even when the two input signals have different potentials. The difference of the two inputs are referred to as an offset voltage. When the offset voltage is V.sub.OFF, the output when the offset voltage is generated is given by the equation (1): EQU V.sub.OUT =G{V.sub.IN1 (V.sub.IN2 +V.sub.OFF)}+V.sub.REF ( 1)
When the offset voltage V.sub.OFF is generated, the output in accordance with the difference between the V.sub.IN1 and V.sub.IN2 is not obtained. This causes an operational error of the voltage comparator. Thus, it is desirable to suppress the generation of the offset voltage V.sub.OFF.
In contrast, as shown in FIG. 4, the conventional voltage comparator is provided with the offset compensating circuit 10 for compensating the offset voltage. The offset compensating circuit 10 is provided in the preceding stage of the differential amplifier 20, and is provided with transfer switches 11 and 12. The transfer switch 11 transfers and outputs (1) the potential V.sub.IN1 or (2) the reference voltage V.sub.REF from a reference voltage source 15. The transfer switch 12 transfers and outputs (a) the potential V.sub.IN2 or (b) the reference voltage V.sub.REF.
In the above voltage comparator, an offset compensating operation is carried out by the offset compensating circuit 10 prior to a voltage comparing operation.
In the offset compensating operation, first, the transfer switches 11 and 12 are respectively switched on the side of the reference voltage source 15, and an input-output switch 13 is turned on. The input-output switch 13 is provided on the output side of the transfer switch 12 via an offset compensating capacitor 14. Also, a high level control signal S is supplied from a control terminal 6 to a switch circuit 40 provided in an output stage of the voltage comparator. This turns on MOS transistors 41 and 42 constituting a transfer gate in the switch circuit 40.
Under these conditions, the reference voltage V.sub.REF is inputted to the input terminal 1 of the voltage comparator. Also, since the input-output switch 13 is turned on, the potential of the input terminal 2 takes the same value as the output potential of the output terminal 3. Namely, the following relations are established: EQU V.sub.IN1 =V.sub.REF EQU V.sub.IN2 =V.sub.OUT
These can be combined with the equation (1) so as to represent the output by the equation: ##EQU1## Here, since G&gt;1 in general, the term {G/(1+G)}.apprxeq.1. Thus, the above equation can be simplified to: EQU V.sub.OUT =V.sub.REF -V.sub.OFF
Specifically, as shown in FIG. 4, the potential of the terminal of the offset compensating capacitor 14 on the side of the differential amplifier 20, namely, the potential of a point P.sub.3 is V.sub.REF -V.sub.OFF, and the potential of the terminal of the offset compensating capacitor 14 on the side of the transfer switch 12, namely, the potential of a point P.sub.4 is V.sub.REF. Thus, the offset compensating capacitor 14 accumulates a charge in accordance with V.sub.OFF which is a potential difference across the offset compensating capacitor 14. Here, when V.sub.OFF &gt;0, the potential of the point P.sub.3 becomes lower than the potential of the point P.sub.4 by the amount of V.sub.OFF, and when V.sub.OFF &lt;0, the potential of the point P.sub.3 becomes higher than the potential of the point P.sub.4 by the amount of V.sub.OFF.
In the offset compensating operation, the voltage comparator functions as an operational amplifier. Thus, by turning on the switch circuit 40 so as to connect a phase compensating capacitor 32 between the input and the output of an amplifier transistor 31, the generation of oscillation can be suppressed, thereby permitting to stabilize the operation of the voltage comparator functioning as the operational amplifier.
After the offset compensating operation is carried out in the described manner, the voltage comparing operation is carried out. When the operation of the voltage comparator is shifted to the voltage comparing operation, the transfer switches 11 and 12 are respectively switched on respective sides of the input terminals 1 and 2, the input-output switch 13 is turned off, and the control signal S becomes a low level.
Here, because a charge for the amount of V.sub.OFF is accumulated in the offset compensating capacitor 14, when the potentials V.sub.IN1 and V.sub.IN2 are respectively supplied, as inputs for the voltage comparator, to the input terminals 1 and 2, the potential (V.sub.IN2 -V.sub.OFF) is supplied to the input terminal 2 equivalently. Thus, in this case, the output is given by the equation: ##EQU2##
As described, by providing the voltage comparator with the offset compensating circuit 10, it is possible to cancel the error of the output voltage due to the offset voltage.
Also, in the voltage comparing operation, by turning off the switch circuit 40 so as to disconnect the phase compensating capacitor 32 from the input and the output of the amplifier transistor 31, it is possible to widen a frequency band, and to increase the operation speed.
Note that, Japanese Unexamined Patent publication No. 43913/1987 (Tokukaishou 62-43913) discloses (1) the function as the operational amplifier and as the voltage comparator and (2) the phase compensating capacitor 32 and the switch circuit 40. The offset compensation, the phase compensating capacitor 32, and the switch circuit 40 are also disclosed in "A Continuously Variable Slope Adaptive Delta Modulation Codec System" in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-18, NO. 6, DECEMBER 1983 p.698.
In the case where the circuit of FIG. 4 is adopted as the voltage comparator, there is a case where the switch circuit 40 cannot be turned off even when the control signal S is made a low level in order to turn off the switch circuit 40. In such a case, it is possible that the distortion of the output V.sub.OUT is caused. The following will describe such a case in detail.
In the case where, for example, the power source voltage V.sub.DD supplied to a power source terminal 4 is 3 V, the power source voltage V.sub.SS supplied to a power source terminal 5 is 0 V, and the reference voltage V.sub.REF is 1.5 V, for the offset compensating operation, when the transfer switches 11 and 12 are respectively switched on the side of the reference voltage source 15, the input-output switch 13 is turned on, and the control signal S is a high level, the potential of the terminal of the phase compensating capacitor 32 on the side of the switch circuit 40, namely, the potential of a point P.sub.1 becomes substantially 1.5 V (V.sub.REF -V.sub.OFF).
Here, when the potential of the phase compensating capacitor 32 on the side of the output terminal of the differential amplifier 20, namely, the potential of a point P.sub.2 is, for example, 0.8 V, a potential difference of 0.7 V is generated across the phase compensating capacitor 32. For this reason, a charge in accordance with the potential difference is accumulated in the phase compensating capacitor 32. This makes the potential of the point P.sub.1 higher than the potential of the point P.sub.2 by the amount of 0.7 V.
Further, when the operation of the voltage comparator is then shifted to the voltage comparing operation by making the switch control signal S a low level such that the potential of the point P.sub.2 becomes 2.8 V when the input of the input terminal 1 is larger than the input of the input terminal 2, because the potential difference of 0.7 V is also generated in this case across the phase compensating capacitor 32, the potential of the point P.sub.1 becomes 3.5 V.
A P-type MOS transistor 42 constituting the switch circuit 40 has a structure shown in FIG. 5. In the case where the MOS transistor 42 is to be provided on a P-type wafer substrate 60, the MOS transistor 42 is formed on a region of an N-well 61. In this case, because the low level control signal S is inverted by an inverter 34 so as to be inputted, a voltage of 3 V is applied to the gate electrode of the MOS transistor 42. Also, as mentioned above, the potential of the terminal of the MOS transistor 42 connected to the point P.sub.1 is 3.5 V. This makes the potential of the terminal of P.sub.1 higher than the potential of the gate electrode, thereby turning on the MOS transistor 42 (although not completely necessarily).
As described, in the case where the circuit of FIG. 4 is adopted as the voltage comparator, there is a case where the MOS transistor 42 is not turned off completely even when the switch control signal S is made a low level in order to turn off the switch circuit 40. In such a case, the switch circuit 40 is not turned off completely.
In the case where the switch circuit 40 is not turned off completely, the current from a constant current source 33 flows to the switch circuit 40. This distorts the output signal of the output terminal 3. For example, as shown in FIG. 6, in the case where the output signal of the differential amplifier 20 has a waveform which rises from V.sub.1 to V.sub.2 at a time T.sub.1, the actual signal outputted from the output terminal 3 has a distorted waveform which does not rise spontaneously from V.sub.3 to V.sub.4, as shown by the curve in FIG. 7.